The d.c. characteristics are computed for pnp polysilicon emitter transistors (PETs) in which a thin insulating layer is incorporated in the emitter structure. Both devices with, and without, a post-polysilicon deposition annealing treatment are modeled. The effects of the annealing are taken to be a reduction in the insulator thickness and the creation of a p-type monosilicon emitter region. The simulations reveal that moderate current gains, around 300, are possible with these devices.
Solid State Electronics
Department of Electronics

Laser, A.P., Chu, K.M., Pulfrey, D.L., Maritan, C.M., & Tarr, N.G. (1990). An investigation of pnp polysilicon emitter transistors. Solid State Electronics, 33(7), 813–818. doi:10.1016/0038-1101(90)90060-R