Quasi-Newton methods are the most widely used methods to find local maxima and minima of functions in various engineering practices. However, they involve a large amount of matrix and vector operations, which are computationally intensive and require a long processing time. Recently, with the increasing density and arithmetic cores, field programmable gate array (FPGA) has become an attractive alternative to the acceleration of scientific computation. This paper aims to accelerate Davidon-Fletcher-Powell quasi-Newton (DFP-QN) method by proposing a customized and pipelined hardware implementation on FPGAs. Experimental results demonstrate that compared with a software implementation, a speed-up of up to 17 times can be achieved by the proposed hardware implementation.

Additional Metadata
Keywords field programmable gate array, hardware acceleration, quasi-Newton method
Persistent URL dx.doi.org/10.1007/s12209-016-2870-0
Journal Transactions of Tianjin University
Citation
Liu, Q. (Qiang), Sang, R. (Ruoyu), & Zhang, Q.J. (2016). FPGA-based acceleration of Davidon-Fletcher-Powell quasi-Newton optimization method. Transactions of Tianjin University, 22(5), 381–387. doi:10.1007/s12209-016-2870-0