Yield analysis and optimization of VLSI interconnects in multichip modules
In the manufacturing process of MCMs, tolerances in VLSI interconnects and material properties lead to variations in critical interconnect performances which in turn can result in reduced MCM yield. This paper presents a new CAD approach integrating multidimensional correlated Monte-Carlo analysis and l1 optimization with lossy transmission line network simulations. It is implemented in a CAD framework for statistical analysis and yield optimization of high-speed VLSI interconnects. Physical/geometrical based hierarchical Monte-Carlo analysis and yield optimization examples are presented.
|Conference||Proceedings of the 1993 IEEE Multi-Chip Module Conference - MCMC-93|
Zhang, Q.J, & Nakhla, M.S. (1993). Yield analysis and optimization of VLSI interconnects in multichip modules. In Proceedings 1993 IEEE Multi-Chip Module Conference (pp. 160–163).