Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique
The common methods for interconnect delay estimation rely upon an RC tree model. These methods are not adequate for high-speed or printed circuit board applications where more elaborate interconnect models are required. The models in this case may contain general RLC lumped and distributed networks. The recently published asymptotic waveform evaluation (AWE) technique provides a generalized approach to lumped RLC circuit response approximations. In addition, more accurate results compared with the RC tree methods can be obtained at an incremental cost in CPU time. However, with higher signal speeds, the electrical lengths of interconnects can become a significant fraction of a wavelength. Consequently, the conventional lumped-impedance interconnect model is not adequate in this case. Two new results are described in this paper: 1) Generalization of the AWE method to handle interconnect models which contain distributed elements. 2) Application of the generalized AWE technique to the important case where the distributed elements can be modeled as lossy coupled transmission lines. The generalized AWE technique is useful for both delay and crosstalk estimation and can be used to evaluate transient responses of high-speed interconnect circuits with negligible error compared with conventional circuit simulators such as SPICE while being two to three orders of magnitude faster.
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
Tang, T.K. (Tak K.), & Nakhla, M.S. (1992). Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(3), 341–352. doi:10.1109/43.124421