This paper describes a delta-sigma (∆-∑) modulation and fractional-N frequency division technique to perform indirect digital frequency synthesis based on the use of a phase-locked loop (PLL). The use of ∆-∑ modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques.
IEEE Journal of Solid-State Circuits
Department of Electronics

Riley, T.A.D. (Tom A.D.), Copeland, M.A. (Miles A.), & Kwasniewski, T. (1993). Delta-Sigma Modulation in Fractional-N Frequency Synthesis. IEEE Journal of Solid-State Circuits, 28(5), 553–559. doi:10.1109/4.229400