This work presents a robust method of implementing a Phase-Locked Loop (PLL). The stability of traditional PLLs currently in use is majorly dependent on the balanced conditions of the grid voltage, which is not always the case. The stability of the strategy being proposed, however, is independent of the symmetry of the grid voltage. When the grid voltage is in phase with the PLL output voltage, the time value of their zero-crossing is the same; conversely, when they fall out phase, the time value of their zero-crossing differs. Phase detection is done using a counter that feeds a PI controller with an error value proportional to this difference in time of zero-crossing; the controller drives the error to zero in time, locking both signals. This implementation is benchmarked against two conventional strategies, and its superior performance under practical grid voltage distortions is confirmed by simulation results.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ISIE.2016.7744955
Conference 25th IEEE International Symposium on Industrial Electronics, ISIE 2016
Citation
Chaoui, H, & Okoye, O. (Okezie). (2016). Simple and robust three-phase Phase-Locked Loop algorithm under grid voltage uncertainties. In IEEE International Symposium on Industrial Electronics (pp. 586–591). doi:10.1109/ISIE.2016.7744955