A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5 μm CMOS gate array technology.

Journal of VLSI Signal Processing
Department of Electronics

Szwarc, V., Desormeaux, L., Wong, W., Yeung, C.P.S., Chan, C.H., & Kwasniewski, T. (1994). A chip set for pipeline and parallel pipeline FFT architectures. Journal of VLSI Signal Processing, 8(3), 253–265. doi:10.1007/BF02106450