Manufacturing complexities due to FinFET's three-dimensional structure and reduced critical dimensions have caused new challenges in achieving reliable device testing. Gate oxide short (GOS) is one of the defects that requires a thorough investigation due to its complexity in 3D transistors and its significant impact on circuit reliability. In this paper, we present a comprehensive study on the transistor defect characteristics as we introduce pinholes in the gate oxide of rectangular fin and trapezoidal fin shape structures. The pinholes are represented by small cuboid cuts of various sizes located along the fin height and channel length. Our analysis is performed with the aid of Synopsys' Sentaurus TCAD tools. The results presented in this paper can lead to the development of more realistic analytical GOS defect model for circuit level simulation.

Additional Metadata
Keywords Defect, FinFET, Gate oxide short, Leakage, Pinhole
Persistent URL dx.doi.org/10.1109/VTS.2017.7928960
Conference 35th IEEE VLSI Test Symposium, VTS 2017
Citation
Dibaj, R. (Roya), Al-Khalili, D. (Dhamin), & Shams, M. (2017). Comprehensive investigation of gate oxide short in fin FETs. In Proceedings of the IEEE VLSI Test Symposium. doi:10.1109/VTS.2017.7928960