A 1.25 GHz monolithic CMOS PLL clock synthesis unit was designed for data communications. The monolithic PLL consists of a ring oscillator, divider, phase/frequency detector, charge pump and on-chip loop filter. The voltage controlled oscillator incorporates a quadrature output ring structure with sub-feedback loop embedded to speed up the circuit. The design accommodates process, supply voltage and temperature variations. The PLL has been fabricated in a 0.35 μm CMOS process, occupies an active area of 1 mm 2, and consumes 100 mW power at 3.3 V.

Additional Metadata
Conference Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
Citation
Sun, Lizhong, & Kwasniewski, T. (1999). 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications. Presented at the Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99.