This paper presents the design consideration of high order digital ΔΣ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC implementation and exhibits high potential for a gigahertz range, low-power monolithic CMOS frequency synthesizer.

Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
Carleton University

Sun, Lizhong, Lepley, Thierry, Nozahic, Franck, Bellissant, Arnaud, Kwasniewski, T, & Heim, Barry. (1999). Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. Presented at the Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99.