A second-order double-sampled analog-to-digital ΣΔ modulator is implemented in a 0.25 μm fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect than traditional bulk CMOS and the threshold voltage and the supply voltage can be lowered for low power application.

Additional Metadata
Conference The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference
Citation
Swaminathan, Ashok, Fong, Neric, Lauzon, Phil, Yang, Hong-Kui, Maliepaard, Mike, Plett, C, & Snelgrove, Martin. (1999). Low power ΣΔ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 μm SOI CMOS technology. Presented at the The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference.