A high frequency analog IC testing technique using a periodic input stimuli and a sequential undersampling algorithm has been developed. This algorithm overcomes many of the loading problems associated with high speed analog signal testing. The utility of the undersampling technique was shown in previous work using a 1.2 μm CMOS prototype IC. This paper expands that work by improving the performance of the original sampling circuits, investigating the possibility of generating control signals on-chip to reduce test cost, and developing a structured analog Design For Testability (DFT) approach. This approach can be used for high speed testing and is based upon undersampling techniques used in sampling oscilloscopes and mixed-signal testers.