A 1.9GHz monolithic superheterodyne receiver front-end with 300MHz IF, on-chip tunable image reject filter and VCO is presented. The receiver was fabricated on a 0.5μm bipolar process. The 2.2GHz VCO was realized with ground-shielded inductors. The performance is as follows: conversion gain: 25.6dB, noise figure: 4.5dB, image rejection: 65dB, and phase noise of -103dBc/Hz at 100kHz offset. The LO-IF isolation improved compared to a previously fabricated front-end with off-chip VCO. This receiver front-end has NF, linearity, and phase noise suitable for DCS-1800.

Additional Metadata
Conference 2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Citation
Rogers, J, Macedo, Jose A., & Plett, C. (2000). Completely integrated 1.9 GHz receiver front-end with monolithic image reject filter and VCO. Presented at the 2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.