An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

Additional Metadata
Keywords Current-mode (CM) drivers, Delays, Driver circuits, Estimation, high-speed links, Jitter, power delivery networks (PDNs), Power supplies, power supply noise, power supply-induced jitter (PSIJ), Switches, time interval error (TIE).
Persistent URL dx.doi.org/10.1109/TVLSI.2017.2760010
Journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Citation
Tripathi, J.N. (Jai Narayan), Achar, R, & Malik, R. (Rakesh). (2017). Fast Analysis of Time Interval Error in Current-Mode Drivers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. doi:10.1109/TVLSI.2017.2760010