The results of a comprehensive investigation into the characteristics and optimization of Inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extncts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in melallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model aecuncy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technolocies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

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Keywords Computational modeling, Inductors, Integrated circuit modeling, Silicon, Solid modeling, Spirals, Substrates
Persistent URL dx.doi.org/10.1109/9780470545492.ch7
Citation
Long, J.R. (John R.), & Copeland, M.A. (2003). The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. In Phase-Locking in High-Performance Systems: From Devices to Architectures (pp. 77–88). doi:10.1109/9780470545492.ch7


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