A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
IEEE Journal of Solid-State Circuits , Volume 36 - Issue 6 p. 910- 916
A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-μm CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply.
|Analog integrated circuits, Clock generation, Frequency synthesizer, Phase-locked loop|
|IEEE Journal of Solid-State Circuits|
|Organisation||Department of Electronics|
Sun, L. (Lizhong), & Kwasniewski, T. (2001). A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. IEEE Journal of Solid-State Circuits, 36(6), 910–916. doi:10.1109/4.924853