10Gb/s ATM data synchroniser
A data synchronizer based on an analog controlled data delay driven by a clock to data phase detector is reported. Fabricated in HRT it runs at 10 Gb/s with 200 ps delay range. Testing has shown that offsets can occur between the 'recenter' voltage and the middle of the delay control range, so a second generation design, currently in processing, has a recenter trim control. It also has a slightly increased delay range to improve performance margins. Notwithstanding the somewhat limited circumstances under which this chip can be used, it is a worthwhile addition to the devices available to systems designers.
|Conference||Proceedings of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium|
Wong, Thomas Y.K. (Thomas Y K), Sitch, John (John), & McGarry, S. (1995). 10Gb/s ATM data synchroniser. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 49–51).