Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits
This paper presents two approaches for simulation of large interconnect networks with linear/nonlinear terminations. The first approach is suitable in forming macromodels of interconnect networks in order to use them repeatedly in different configurations. The second approach is a nonlinear time-domain circuit reduction technique that reduces the whole interconnect network including the nonlinear/linear terminations. This method is independent of the number of ports in the system.
|IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging|
|Organisation||Department of Electronics|
Gunupudi, P, Khazaka, R., Dounavis, A., Nakhla, M.S, & Achar, R. (2001). Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits. In IEEE Topical Meeting on Electrical Performance of Electronic Packaging (pp. 259–262).