Additional Metadata
Persistent URL dx.doi.org/10.1049/el:20030075
Journal Electronics Letters
Citation
Zhuang, J. (Jingcheng), Du, Q. (Qingjin), & Kwasniewski, T. (2003). Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator. Electronics Letters, 39(1), 48–50. doi:10.1049/el:20030075