A parameterized model-order reduction algorithm for nonuniform high-speed interconnect with varying design parameters is presented. The constructed reduced-order model (ROM) has a direct time-domain representation, and thus, discretization techniques are not required. The key idea of the new algorithm is to find a common-projection matrix using the integrated-congruence transform (ICT) method that can be used to construct an ROM for any value of the varying parameters. However, the calculated projection matrices using the ICT method are functions of the position along the lines, and thus, finding a common-projection matrix using regular singular-value decomposition (SVD) is not applicable. To address this issue, a Hilbert-space-based SVD is proposed to extract the common-projection matrix.

Additional Metadata
Keywords High-speed interconnects, Integrated circuit interconnections, Integrated circuit modeling, integrated-congruent transform (ICT), Mathematical model, Matrix decomposition, nonuniform interconnects, parametrized model-order reduction (PMOR)., Read only memory, Transforms, Transmission line theory
Persistent URL dx.doi.org/10.1109/TCPMT.2018.2841372
Journal IEEE Transactions on Components, Packaging and Manufacturing Technology
Citation
Farhan, M.A. (Mina A.), & Nakhla, M.S. (2018). Parametric Order Reduction of Nonuniform Interconnect Circuits Using Integrated Congruence Transform. IEEE Transactions on Components, Packaging and Manufacturing Technology. doi:10.1109/TCPMT.2018.2841372