An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.

High-speed links, power delivery networks (PDN), power supply induced jitter (PSIJ), power supply noise, voltage-mode drivers
IEEE Transactions on Components, Packaging and Manufacturing Technology
Department of Electronics

Tripathi, J.N. (Jai Narayan), Achar, R, & Malik, R. (Rakesh). (2017). Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ). IEEE Transactions on Components, Packaging and Manufacturing Technology, 7(10), 1691–1701. doi:10.1109/TCPMT.2017.2711480