CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications
We report on a CMOS inductorless VCO design with an emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three structures- one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The measurement results of three VCOs implemented in 1.2 J.1m CMOS technology verify the simulation predictions. The simplest veo architecture exhibits 926-MHz operation with -83 dBclHz phase noise (100 kHz carrier offset) and 5 mW (5 volts) power consumption.
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Thamsirianunt, M. (Manop), & Kwasniewski, T. (1998). CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications. In Integrated Circuits for Wireless Communications (pp. 441–444). doi:10.1109/9780470544952.ch6