2004-12-01
Design and implementation of a reconfigurable polyphase-fft system
Publication
Publication
Presented at the
Proceedings of the IASTED International Conference on Circuits, Signals, and Systems (November 2004)
A reconfigurable system design and implementation of Polyphase-FFT circuits for multicarrier wireless applications is presented. The proof of concept circuit realization can be configured to compute IFFT-Polyphase or Polyphase-FFT algorithms for 8, 16, and 32 subcarriers. Furthermore, the system-on-chip circuit can be configured for full-duplex operation and can implement both IFFT-Polyphase and Polyphase-FFT algorithms for 8 or 16 subcarriers. The throughput, hardware requirements, and power consumption for the reconfigurable circuits are presented and compared with conventional realizations.
| Additional Metadata | |
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| Multicarrier, Polyphase-FFT algorithm, Reconfigurable architecture, System-on-chip | |
| Proceedings of the IASTED International Conference on Circuits, Signals, and Systems | |
| Organisation | Department of Electronics |
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Ho, H., Szwarc, V., & Kwasniewski, T. (2004). Design and implementation of a reconfigurable polyphase-fft system. Presented at the Proceedings of the IASTED International Conference on Circuits, Signals, and Systems.
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