1999-01-01
A low power ΣΔ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 μm SOI CMOS technology
Publication
Publication
Presented at the
25th Annual IEEE International Silicon-on-Insulator Conference, SOI 19999 (October 1999), Rohnert Park
A second-order double-sampled analog-to-digital ΣΔ modulator is implemented in a 0.25 μm fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.
| Additional Metadata | |
|---|---|
| Persistent URL | dx.doi.org/10.1109/SOI.1999.819835 |
| Conference | 25th Annual IEEE International Silicon-on-Insulator Conference, SOI 19999 |
| Citation |
Swaminathan, A. (A.), Fong, N. (N.), Lauzon, P. (P.), Yang, H.-K. (Hong-Kui), Maliepaard, M. (M.), Plett, C, & Snelgrove, M. (M.). (1999). A low power ΣΔ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 μm SOI CMOS technology. In 1999 IEEE International SOI Conference, SOI 1999 - Proceedings (pp. 14–15). doi:10.1109/SOI.1999.819835
|