In this paper we address the important problem of instruction fetch for future wide issue superscalar processors. Our approach focuses on understanding the interaction between software and hardware techniques targeting an increase in the instruction fetch bandwidth. That is the objective, for instance, of the Hardware Trace Cache (HTC).We design a profile based code reordering technique which targets a maximization of the sequentially of instructions, while still trying to minimize instruction cache misses. We call our software approach, Software Trace Cache (STC). Copyright

Additional Metadata
Persistent URL dx.doi.org/10.1145/2591635.2667175
Conference 25th ACM International Conference on Supercomputing, ICS 2014
Citation
Ramirez, A, Larriba-Pey, J.-L. (Josep-L.), Navarro, C. (Carlos), Torrellas, J. (Josep), & Valero, M. (Mateo). (2014). Software trace cache. In Proceedings of the International Conference on Supercomputing (pp. 261–268). doi:10.1145/2591635.2667175