A precision CMOS analog cubing circuit
The practical implementation of a precision analog cubing function in 0.18μm CMOS technology is presented. The cubing circuit consumes less power, has a smaller layout area, and achieves a higher operating frequency than previously published designs. The circuit advantageously utilizes the non-square-law current-voltage characteristics of deep-submicron CMOS to achieve a precise cubing function. The effects of component mismatch on the output error are explored. A common-centroid layout is used to reduce component mismatch due to linear process, temperature, and stress gradients. The cubing circuit has a total DC current draw of 6.3mA from a single 1.8V supply. The maximum error between the simulated and ideal cubing response is ±0.7mV over the output range ±30mV for operating frequencies up to 1GHz.
|Conference||Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004|
Shearer, F. (Fiona), & MacEachern, L. (2004). A precision CMOS analog cubing circuit. Presented at the Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004.