Interconnect modeling and simulation
With the rapid developments in VLSI technology, design, and CAD techniques, at both the chip and package level, the central processor cycle times are reaching the vicinity of 1 ns and communication switches are being designed to transmit data that have bit rates faster than 1 Gb/s. The ever-increasing quest for high-speed applications is placing higher demands on interconnect performance and highlights the previously negligible effects of interconnects (Fig. 10.1), such as ringing, signal delay, distortion, reflections, and crosstalk.1-33 In addition, the trend in the VLSI industry toward miniature designs, low power consumption, and increased integration of analog circuits with digital blocks has further complicated the issue of signal integrity analysis. Fig. 10.2 describes the effect of scaling of chip on the global interconnect delay. As seen, the global interconnect delay grows as a cubic power of the scaling factor.1 It is predicted that interconnects will be responsible for nearly 70 to 80% of the signal delay in high-speed systems.
Nakhla, M.S, & Achar, R. (2003). Interconnect modeling and simulation. In Design Automation, Languages, and Simulations (pp. 10‐1–10‐30). doi:10.1201/9780203009284