2018
Efficient Jitter Analysis for a Chain of CMOS Inverters
Publication
Publication
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method [J. N. Tripathi, R. Achar, and R. Malik, “Efficient modeling of power supply induced jitter in voltage-mode drivers (EMPSIJ),” IEEE Trans. Compon., Packag.Manuf. Technol., vol. 7, no. 10, pp. 1691–1701, Oct. 2017.] is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
| Additional Metadata | |
|---|---|
| CMOS inverters, ground bounce, high-speed interconnects, jitter, power delivery network (PDN), power integrity, power supply induced jitter (PSIJ), power supply noise | |
| doi.org/10.1109/TEMC.2018.2878354 | |
| IEEE Transactions on Electromagnetic Compatibility | |
| Organisation | Department of Electronics |
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Tripathi, J.N. (Jai Narayan), Arora, P. (Puneet), Shrimali, H. (Hitesh), & Achar, R. (2018). Efficient Jitter Analysis for a Chain of CMOS Inverters. IEEE Transactions on Electromagnetic Compatibility. doi:10.1109/TEMC.2018.2878354
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