This work presents a shared fractional-N synthesizer used by two dual-band 802.11 radios integrated on a single chip for 2 × 2 multiple-input multiple-output (MIMO) applications. Additional 2 × 2 MIMO chips can be used in a system by phase synchronizing the signal paths through a bidirectional LO porting scheme developed for this application. This synthesizer was fully integrated with the exception of an off-chip loop filter. The synthesizer is a ΔΣ-based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in the IEEE 802.11a/b/g and Japanese WLAN standards. The radio uses a variable IF frequency so that both the RF LO and IF LO can be derived from a single synthesizer saving chip area and power. The synthesizer includes a programmable second/third-order ΔΣ noise shaper, a phase frequency detector, a differential charge pump, and a 6-bit multimodulus divider (MMD). The nominal jitter from 100 Hz to 10 MHz is 0.63-0.86° rms in the 5-GHz band and 0.35-0.43° rms in the 2.4-GHz band. The maximum frequency deviation of the synthesizer when enabling the transmitter is less than 150 kHz and the frequency error settles to 2 kHz in less than 12 μs. For MIMO applications requiring more than two full paths, a single synthesizer on one die can be used to generate the LOs for all other radios integrated in different dies.

Additional Metadata
Keywords 802.11, Fractional-N synthesizer, MIMO, RFIC, SiGe, Sigma-delta modulator, Voltage-controlled oscillators, Wireless communications, WLAN
Persistent URL dx.doi.org/10.1109/JSSC.2005.843604
Journal IEEE Journal of Solid-State Circuits
Citation
Rogers, J, Dai, F.F. (Foster F.), Cavin, M.S. (Mark S.), & Rahn, D.G. (David G.). (2005). A Multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC. IEEE Journal of Solid-State Circuits, 40(3), 678–688. doi:10.1109/JSSC.2005.843604