This paper presents a compact high performance clock multiplier based on an injection locked ring oscillator (ILRO) with replica oscillator tuning. All cells were synthesized utilizing vendor supplied digital cells and automatically placed and routed to improve scalability and speed up the design process. The ILRO, fabricated in TSMC 65 nm CMOS process technology, occupies 102 μm × 170 μm chip area. At 1.1 V and 1.7 GHz, the measured phase noise for third harmonic injection locking was found to be -128 dBc/Hz at 1 MHz offset. Furthermore, it consumes 11.77 mW and achieves 200 fs RMS jitter (1 kHz to 40 MHz) and 86 MHz locking bandwidth.

Additional Metadata
Keywords clock multiplier, DCO, injection locking, PVT calibration, ring oscillator, synthesized
Persistent URL dx.doi.org/10.1109/ISCAS.2018.8351243
Conference 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Citation
Abou-El-Kheir, N.T. (Nahla T.), Mason, R, Li, M. (Mingze), & Yagoub, M.C.E. (M. C.E.). (2018). A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator. In Proceedings - IEEE International Symposium on Circuits and Systems. doi:10.1109/ISCAS.2018.8351243