New charge-steering latches are proposed and simulated in 28nm FD-SOI CMOS for use in wireline transceivers. Three new latches demonstrate power savings of up to 40% when compared to conventional charge-steering latches. These latches achieve power savings through the addition of a switch in the pMOS cross-coupled pair which eliminates transistor power consumption when they are not required. All new latches demonstrate the ability to operate at data rates exceeding 28Gb/s, enabling a 56Gb/s SERDES when used in a half-rate architecture. Simulation results are also verified through analytical expressions.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Department of Electronics

Pike, J. (Jacob), Parvizi, M. (Mahdi), Ben-Hamida, N. (Naim), Aouini, S. (Sadok), & Plett, C. (2018). New Charge-Steering Latches in 28nm CMOS for Use in High-Speed Wireline Transceivers. In Proceedings - IEEE International Symposium on Circuits and Systems. doi:10.1109/ISCAS.2018.8351013