In this paper, a novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm (also referred to as max-sum or max-product) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes, The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. To demonstrate the functionality of the proposed design, simulation results based on TSMC 0.18μm CMOS technology for a (7,4) Hamming code are also presented.

Additional Metadata
Keywords Analog Circuit, Analog CMOS, Analog Iterative Decoder, Asynchronous Iterative Decoding, Iterative Decoding, Low-Density Parity-Check Codes, Min-Sum Decoding, Soft Decoding, Turbo codes
Conference Proceedings of the 2003 ACM Great Lakes Symposium on VLSI
Citation
Hemati, S. (Saied), & Banihashemi, A. (2003). Iterative decoding in analog CMOS. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 15–20).