This paper presents the FPGA implementation of a number of popular decoding algorithms for a regular rate-1/2 low density parity check code with block length 504 bits. The so-called min-sum (MS) algorithm and two of its variants, known as MS with successive relaxation (SR-MS) and MS with unconditional correction (MS-UC), are implemented. We implement the algorithms on a Xilinx XC2VP100 FPGA device with 4-bit quantization. We show that for MS-UC, the circuit utilization increases by about 2% compared to standard MS and that the throughput is the same as that of MS. For SR-MS, the device utilization is increased by about 26% and the throughput is decreased by approximately 20% compared to standard MS. While the throughput and the area and power consumption of our implementation is comparable to the most recent FPGA implementations of LDPC decoders, ours is the first attempt at implementing an iterative decoding algorithm with memory (SR-MS).

dx.doi.org/10.1109/BSC.2008.4563210
24th Biennial Symposium on Communications, BSC 2008
Department of Systems and Computer Engineering

Tolouei, S. (Sina), & Banihashemi, A. (2008). FPGA implementation of variants of min-sum algorithm. In 24th Biennial Symposium on Communications, BSC 2008 (pp. 80–83). doi:10.1109/BSC.2008.4563210