Full CMOS min-sum analog iterative decoder
A novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. An example decoder design, based on TSMC 0.18 μm CMOS technology is also presented for a (7,4) Hamming code.
|Proceedings 2003 IEEE International Symposium on Information Theory (ISIT)|
|Organisation||Department of Systems and Computer Engineering|
Hemati, S. (Saied), & Banihashemi, A. (2003). Full CMOS min-sum analog iterative decoder. In IEEE International Symposium on Information Theory - Proceedings.