2003-12-01
A current-mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders
Publication
Publication
Presented at the
2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003 (December 2003), Sharjah
A new current-mode maximum winner-take-all (Max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about Veff (V ml) and 2Veff(2Vsat), respectively. Because of cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13μm UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.
| Additional Metadata | |
|---|---|
| Persistent URL | dx.doi.org/10.1109/ICECS.2003.1301962 |
| Conference | 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003 |
| Citation |
Hemati, S. (Saied), & Banihashemi, A. (2003). A current-mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 4–7). doi:10.1109/ICECS.2003.1301962
|