In the context of the IEEE 1588 Precision Time Protocol (PTP), estimating the delay's bias is a problem that appears in both one-way (using transparent devices) or two-way message exchange mechanisms. For estimating the offset via the two-way message exchange mechanism, it is usually assumed that the expected value of delays in forward and reverse directions are equal. However, this is not a realistic assumption for packet-based wide area networks, where delays in down-link and up-link directions may have a significant difference. In this work, we propose a solution to estimate the random delay's bias and improve the synchronization accuracy of IEEE 1588. Our method is easy to implement and is compatible with the current version of the protocol. We compared our results to no bias correction and the Boot-strap method. In addition to the improvement in synchronization accuracy, our method allows us to update the slave clock recursively. The proposed method works well even in the presence of large frequency offsets and can also be implemented by using different filters.

Additional Metadata
Keywords Asymmetric delays, Boot-strap method, clock synchronization, Gamma PDV, IEEE 1588, two-way message exchange mechanism
Persistent URL dx.doi.org/10.1109/TNET.2015.2462772
Journal IEEE/ACM Transactions on Networking
Citation
Hajikhani, M.J. (Mohammad Javad), Kunz, T, & Schwartz, H.M. (2016). A Recursive Method for Clock Synchronization in Asymmetric Packet-Based Networks. IEEE/ACM Transactions on Networking, 24(4), 2332–2342. doi:10.1109/TNET.2015.2462772