A fast and efficient method is proposed for placement of decoupling capacitors on printed circuit boards (PCB) with resonant parallel planes. Using the pin impedance as a fitness function, a genetic algorithm (GA) based method is used for simultaneous optimization of capacitors' placement with respect to ball-grid array (BGA) pin fields. The proposed method applies to practical PCB designs without restriction on the number of power pins or planar geometry. The developed algorithm is tested on an industrial example in comparison to a numerical electromagnetic (EM) simulator. The results are shown to agree well while significant speed-up is obtained with the proposed algorithm.

Additional Metadata
Keywords decoupling capacitors, Power delivery network (PDN), power integrity
Persistent URL dx.doi.org/10.1109/EDAPS.2018.8680884
Conference 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018
Citation
Erdin, I. (Ihsan), & Achar, R. (2019). Multi-pin Optimization of Decoupling Capacitors on Practical Printed Circuit Boards. In IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018. doi:10.1109/EDAPS.2018.8680884