A FIR filter for pre-emphasis has been used to counteract inter-symbol interference (ISI) in high-speed backplane data transmission. A novel circuit design for retiming data using a half-rate clock for the taps of a FIR filter is proposed. HSPICE simulation results for CMOS 0.18 um technology verify that the jitter of PRBS15 (215-1) data at rate of 6.25 Gbps with a pre-emphasis value of 50% can be reduced to approximately 14 psec and thereby alleviating the requirement on clock frequency.

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Conference 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Citation
Li, M. (Miao), Kwasniewski, T, & Noel, P. (Peter). (2004). Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis. Presented at the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology.