Modeling and optimization of mixed logic circuits: The CMOS/CPL combination

Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.