The implementation of AES S-boxes is one of the most extensively studied areas of cryptography. In this paper, we propose three new hardware designs for the AES S-box that can serve in the forward, inverse and combined data paths. Each of these designs represents the smallest AES S-box ever proposed in its respective category. We achieve this goal by using new tower field representation over normal bases and optimizing each and every block inside the three proposed architectures. Our complexity analysis and ASIC synthesis results in the CMOS STM 65nm, as well as the NanGate 15nm technologies, show that our designs outperform their counterparts in terms of area and power.

Additional Metadata
Keywords AES S-box, Digital arithmetic, Encryption, Germanium, Logic gates, Normal Basis, Poles and towers, Special issues and sections, Tower Field Representation
Persistent URL dx.doi.org/10.1109/TC.2019.2922601
Journal IEEE Transactions on Computers
Citation
Reyhani-Masoleh, A. (Arash), Taha, M, & Ashmawy, D. (Doaa). (2019). New Low-Area Designs for the AES Forward, Inverse and Combined S-boxes. IEEE Transactions on Computers. doi:10.1109/TC.2019.2922601