Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more. Thus, the overall phase noise contribution is dominated by the POM effect rather than the quantization error. This paper proposes a conjoined-ring Vernier (CRV) TDC with a POM error correction circuit that can eliminate the POM error and its consequent corruption on phase noise performance, making quantization error as being the only contribution of the overall phase noise. Meanwhile, the proposed TDC implementation maintains competitive performance in terms of fine time resolution (3 or 0.8 ps) and a flexible large time-length detection range (12 ns) capability in 40-nm CMOS technology. The CRV structure operates like a phase cutter, which separates the time interval into segments with an identical length of about 160 ps, except the residue segment (<160 ps), which will be the only part that needs to be measured at the finest time resolution. The POM error correction circuit is created by embedding a couple of switches into the CRV structure to form a short-time window (<15 ps). This time window is expected to distinguish the occurrence of the misalignment of the parallel outputs between the loop counter and the Vernier core. The corresponding compensation scheme, including the N-calibration circuit, is developed to correct the linearity.
|, , , , , , , , ,|
|IEEE Journal of Solid-State Circuits|
|Organisation||Department of Electronics|
Wang, T. (Tuoxin), Rogers, J, & Mitric, K. (Krste). (2019). Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs). IEEE Journal of Solid-State Circuits. doi:10.1109/JSSC.2019.2927871