In this paper, a design methodology for an efficient programmable delay line using reduced hardware resources is presented. The proposed methodology is scalable and reuses the given buffer elements multiple times to accomplish the task. A substantial absolute delay required in the system is achieved with an equivalent circuit using limited number of buffers. The novel design of the delay line is compared with the conventional architecture in terms of area, leakage power and process variability. It is demonstrated that the proposed design is better than its predecessors in all dimensions.

buffer delay, Delay cell, delay line
dx.doi.org/10.1109/SaPIW.2019.8781675
23rd IEEE Workshop on Signal and Power Integrity, SPI 2019
Department of Electronics

Bal, A. (Ankur), Tiwari, J.N. (Jeet Narayan), Narayan Tripathi, J. (Jai), & Achar, R. (2019). A Novel Programmable Delay Line for VLSI Systems. In 2019 IEEE 23rd Workshop on Signal and Power Integrity, SPI 2019 - Proceedings. doi:10.1109/SaPIW.2019.8781675