Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects
This paper presents an efficient method for the estimation of jitter due to power supply noise in a chain-of-inverters including the on-chip-interconnects. An analytical noise transfer function from power supply to output is derived based on a small-signal analysis. The estimation of jitter is done using a slope-based semi-analytical approach and the results are compared with the SPICE-based simulations.
|Keywords||clock-network, delay-line, Inverter chain, jitter, power supply noise, time interval error|
|Conference||23rd IEEE Workshop on Signal and Power Integrity, SPI 2019|
Illikkal, M.S. (Muhammed Suhail), Tripathi, J.N. (Jai Narayan), Shrimali, H. (Hitesh), & Achar, R. (2019). Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects. In 2019 IEEE 23rd Workshop on Signal and Power Integrity, SPI 2019 - Proceedings. doi:10.1109/SaPIW.2019.8781638