Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

Illikkal, Muhammed Suhail; Tripathi, Jai Narayan; Shrimali, Hitesh; Achar, Ram

doi:10.1109/SaPIW.2019.8781638

Illikkal, M.S. (Muhammed Suhail), Tripathi, J.N. (Jai Narayan), Shrimali, H. (Hitesh) and R. Achar (Ram)

2019-06-01

Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

Presented at the 23rd IEEE Workshop on Signal and Power Integrity, SPI 2019 (June 2019), Chambery

This paper presents an efficient method for the estimation of jitter due to power supply noise in a chain-of-inverters including the on-chip-interconnects. An analytical noise transfer function from power supply to output is derived based on a small-signal analysis. The estimation of jitter is done using a slope-based semi-analytical approach and the results are compared with the SPICE-based simulations.

Additional Metadata
Keywords	clock-network, delay-line, Inverter chain, jitter, power supply noise, time interval error
Persistent URL	doi.org/10.1109/SaPIW.2019.8781638
Conference	23rd IEEE Workshop on Signal and Power Integrity, SPI 2019
Organisation	Department of Electronics
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Illikkal, M.S. (Muhammed Suhail), Tripathi, J.N. (Jai Narayan), Shrimali, H. (Hitesh), & Achar, R. (2019). Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects. In 2019 IEEE 23rd Workshop on Signal and Power Integrity, SPI 2019 - Proceedings. doi:10.1109/SaPIW.2019.8781638

Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

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Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects

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