2019-07-01
Single ended computational SRAM bit-cell
Publication
Publication
Dual port SRAM plays an important role in maintaining the bandwidth of dataflow between memory and processor. To improve data stability and bandwidth, the memory industry moved from conventional 6 transistor (6T) to 8 transistor (8T) SRAM but compromised on the layout area for additional stability. To address the trade-off between area and reliability, a novel Single Ended 8T SRAM is proposed in this paper along with its static analysis, transient response and power consumption, to observe its efficiency and reliability. The proposed SRAM bit-cell architecture is also capable of in-memory computation, thereby potentially avoiding the Von-Neumann bottleneck problem for some computations. In particular, the proposed SRAM can perform in-memory NAND and NOR operations, and may be useful for low-power and high-performance machine learning and neural network hardware architectures.
Additional Metadata | |
---|---|
doi.org/10.1109/ISSCS.2019.8801735 | |
2019 International Symposium on Signals, Circuits and Systems, ISSCS 2019 | |
Organisation | Department of Electronics |
Kareer, S. (Shobhit), MacEachern, L, Groza, V. (Voicu), & Park, J. (Jeongwon). (2019). Single ended computational SRAM bit-cell. In ISSCS 2019 - International Symposium on Signals, Circuits and Systems. doi:10.1109/ISSCS.2019.8801735
|