Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 μm CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.

Additional Metadata
Persistent URL dx.doi.org/10.1049/el:20052206
Journal Electronics Letters
Citation
Li, M., Wang, S., & Kwasniewski, T. (2005). DFE architectures for high-speed backplane applications. Electronics Letters, 41(20), 1115–1116. doi:10.1049/el:20052206