In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. The result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650ps for a device based on TSMC 0.18μ m technology.

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Conference 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Citation
Wan, Y. (Yuanzhong), & Shams, M. (2005). Optimization of mixed logic circuits with application to a 64-bit static adder. Presented at the 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems.