With the increasing operating frequencies and functionality in modern VLSI designs, the resulting size of circuit equations of high-frequency modules are becoming large. Two-level passive model-reduction based algorithms were recently suggested to obtain compact macromodels for fast transient analysis of large scale VLSI circuits and interconnect networks. However, one of the major issues involved with the current second level reduction algorithms is the high computation expense. In order to overcome this difficulty, this paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms. Necessary formulation and validation examples are given.

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Persistent URL dx.doi.org/10.1109/ICVD.2005.143
Conference 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Saraswat, D., Achar, R, & Nakhla, M.S. (2005). Projection based fast passive compact macromodeling of high-speed VLSI circuits and interconnects. In Proceedings of the IEEE International Conference on VLSI Design (pp. 629–633). doi:10.1109/ICVD.2005.143