To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. This paper compares and analyzes the performance and energy efficiency of various PCGs in a uniform test environment. The test benches are layed out in a standard 0.18 μm CMOS technology and the results are mainly based on post layout simulations.

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Conference 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Citation
Arsalan, M, & Shams, M. (2005). Charge-recovery power clock generators for adiabatic logic circuits. Presented at the 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems.