This paper introduces the implementation of multi-GHz power-aware asynchronous pipelined circuits in MOS Current-Mode Logic (MCML). The C-element and double-edge-triggered flip-flop are implemented in MCML and used in the so-called micropipeline circuits. An input data detector is proposed to place the inactive combinational logic to sleep mode in the asynchronous MCML pipelined circuit. The effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results in a standard 0.18μm CMOS technology, an asynchronous MCML four-stage FIFO demonstrates a throughput of 4 GHz while dissipating 3.7 mW. The MCML C-element dissipates up to four times less power compared to its conventional static CMOS counterpart at the same throughput of 1.9 GHz. The asynchronous MCML pipelined four-bit carry-look ahead adder with the power-saving mechanism reduces the power dissipation by 32% compared to the one without the power-saving mechanism at the same throughput. The power overhead of the input data detector is only 0.23 mW. The input data detector shuts off the stage power in 2 ns and restores the stage in 150 ps after the presence of the new input.

Additional Metadata
Conference 11th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2005
Citation
Kwan, T.W. (Tin Wai), & Shams, M. (2005). Design of high-performance power-aware asynchronous pipelined circuits in MOS Current-Mode Logic. Presented at the 11th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2005.