An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications
Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable micro-architecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications.
|Keywords||Field Programmable Gate Array, Internet-of-Things, Low power, Multi-cycle execution (ME), Partial reconfiguration, Pipeline execution (PE), RISC, Sensor node (SN)|
|Journal||Microprocessors and Microsystems|
Kiat, W.-P. (Wei-Pau), Mok, K.-M. (Kai-Ming), Lee, W.-K. (Wai-Kong), Goh, H.-G. (Hock-Guan), & Achar, R. (2020). An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications. Microprocessors and Microsystems, 73. doi:10.1016/j.micpro.2019.102966